1. Field of the Present Invention
The present invention generally relates to the field of microprocessor based computers and more particularly to organizing and managing buffers in a bus bridge to improve the performance of a computing system.
2. History of Related Art
Microprocessor based computer systems typically employ a variety of adapters or peripheral devices to provide extended capabilities to the system and to decrease the processing load required of the central processor or processors. As computing systems continue to increase in performance and complexity, the number of peripheral devices has increased commensurately often necessitating the use of multiple layers of peripheral busses to accommodate all of the required peripheral devices and to provide expansion capacity to the system user. Typically, specialized circuits or devices generally referred to as bus bridges provide the functionality required to enable the various busses within a system to communicate information. The increased importance of peripheral devices in modern computers, from the simplest consumer oriented machines to high end enterprise systems, has generated increased attention to the performance of peripheral busses and bus bridges. Increasing the number of instructions a central processor can execute per second results in only a marginal increase in system performance if the system's bus bridges and peripheral busses are operating at their performance limits. Typically, however, the ability to improve bus bridge performance is constrained by compatibility concerns. Accommodating the large base of peripheral devices designed according to a preexisting bus specification limits the ability to make changes to any bus bridge design. Accordingly, improvements to a particular bus bridge design should, to the greatest extent possible, be compatible with existing bus protocols.
Because bus bridges may be coupled between busses operating at different clock frequencies or between a bus that is currently accessible and a bus that is busy, bridges routinely implement a pool of storage buffers for temporarily storing transactions in transit from one bus to another. Each storage buffer is typically configured to store any of a variety of transactions. Some bus bridges, such as bridges compliant with the PCI specification, include the capability to merge or combine transactions. Such capabilities, however, are all too commonly underutilized because the buffer pool organization of conventionally designed bridges coupled with constraints imposed by the bus specifications prevent or significantly diminish the opportunities to take advantage of the combining or merging capabilities of the bridge. Moreover, conventional bridge designs and buffer pool organizations in which transactions are stored in a common pool can unnecessarily hamper performance of commonly invoked procedures such as interrupt handling routines by failing to associate buffered transactions with their sources. Without information concerning the origin of buffered transactions, many common procedures are forced, under the constraints of the relevant bus specification, to account for each transaction in the buffer pool, regardless of whether a given transaction is relevant to the procedure. Accordingly, it is highly desirable to implement a bus bridge designed to take greater advantage of opportunities to combine buffered transactions and improve the efficiency of commonly invoked procedures such as interrupt handling while maintaining compatibility with existing bus specifications and protocols.